1. Technical Field
The invention relates to a high-speed optical wide area network (WAN) employing recirculating network topologies such as a shuffle exchange network (SN).
2. Background Art
Many networks discussed in the literature aim to optimize network characteristics at the expense of complicating the implementation. While such networks provide good performance bench marks, they are often difficult to implement with current or near-future technology. Current optical communication networks typically operate at a single frequency in a ring or bus topology. One example is the fiber distributed data interface (FDDI), which is a 100 megabit/sec token ring network. As computational and communications demands increase, such networks are inadequate to handle future demand.
One way to attempt alleviating such inadequacies could be to scale the size of the network, which corresponds to the number of bidirectional host I/O links to the network. FIG. 1 shows an 8-node SN with four of eight I/O links being used. One possible approach to increasing the network capacity with respect to the I/O capacity is to increase the number of SN switching nodes while keeping the number of host connections fixed. In the case of FIG. 1, only half of the I/O capacity of the network is used resulting in a doubling of the network capacity compared to the I/O bandwidth. While this approach does alleviate congestion problems, it does not apply the SN topology in an optimal way. The SN topology provides the minimum hop path for a given number of nodes. The penalty paid for this characteristic is that a deflected packet will incur an additional k hops in reaching its destination, where k is the number of switching node columns. Scaling the network in this way only helps if packet deflection is avoided. If network "hot spots" exist and result in packet deflections, the end result is to increase the latency of deflected packets due to the addition of more node stages when scaling the network in this way. In fact, for such cyclic SN networks, unacceptable delays can be encountered when as little as 15% of the inputs are in simultaneous use, depending upon desired packet destinations. For a cyclic SN, the number of switching nodes is k*2.sup.k, for k switching node stages with 2.sup.k nodes per stage. For FIG. 1, k is equal to two.